1. Field of the invention
The present invention is related to a gated clock design technique by the use of a computer, and more particularly related to a clock supplying circuit and an enable buffer cell, and a computer aided design system and method for clock gated logic circuits and design method thereof and an enable buffer cell.
2. Description of the Prior Art
In recent years, the integration and the chip size of LSIs have dramatically increased to require much power consumption. The gated clock design technique has been developed for the purpose of obtaining the logic circuit designs with low electric power consumption.
The procedure of modifying logic circuits by means of the gated clock design technique is called as xe2x80x9cclock gatingxe2x80x9d in the following explanation. First, the gated clock design as mentioned above will be briefly explained.
FIG. 1 is a partial circuit diagram showing a clocked logic circuit which has not been clock gated. In the same figure, the reference symbols FF0, FF1, . . . FF31 designate 32 D-type flip-flops in the form of a 32 bits data register in combination. The clock input port CK of the respective flip-flop is given the clock signal CLK at the same timing while the data input port D of the respective flip-flop is given data as calculated in the data processing circuit 11 in synchronism with the rising timing of the clock signal CLK.
It is known that the power consumption is increased when the clock signal supplied to the flip-flops rises up or falls down in the operation of the logic circuit of this kind. However, unnecessary power consumption occurs when there is no need for loading data to flip-flops, since the clock signal is continuously input to the flip-flops irrespective of existence of data to be loaded.
FIG. 2 is the circuit diagram of a logic circuit to which the clock gating technique is applied, in which an AND gate 12 is disposed as the gating circuit on the clock line as illustrated in FIG. 2. The AND gate 12 is connected to the enable logic circuit (not shown) for controlling output of the clock signal and for outputting the enable signal E of a logic one or a logic zero to the AND gate 12 in synchronism with the clock signal CLK.
In FIG. 2, when the enable signals E is set a logic one, data is input to the flip-flops in synchronism with the clock signal CLK because the logic product of the enable signals E and the signal CLK is a logic one. On the other hand, when the enable signals E is set a logic zero, data is not input to the flip-flops irrespective of the clock signal CLK taking a logic one because of the logic product of the enable signals E and the signal CLK always remains of a logic zero. Accordingly, when there is no need for loading data to flip-flops, unnecessary power consumption can be avoided by outputting the enable signals E of a logic zero in synchronism with the clock signal CLK.
The power saving efficiency is largely depending upon the actual technique of how to generate the enable signals based upon which storage elements such as registers and memories are selectively given the clock signal. Prior to the present invention, the design of the enable signals has been conducted by manual processes or by CAD systems for automatically generating the enable signals from the control algorithm of the logic circuit.
However, in accordance with the prior art clock gating circuit designing technique, any proposals for generating appropriate enable signals have not been made from the view point of the power saving efficiency. For this reason, it is not confirmed that the enable signals as used are appropriate for the power saving efficiency so that it is often the case that the clock gating circuit designing technique has been conducted with inefficient enable signals.
On the other hand, while the frequency of the clock signal as supplied to the circuits integrated within an LSI chip has been drastically increased, the electric power consumption is also proportionally increased along therewith resulting in difficult problems associated. More specifically speaking, as a result of the increased electric power consumption, the heat as generated tends to exceed the capacity of heat dissipation of the package of an LSI chip. On the other hand, the life time of a battery system for supplying power to the LSI is often shortened by the resultant high temperature.
It is possible to assume that the sources of the power consumption of an LSI chip are located in a data transmission system, a clock system, an I/O system and function modules. Among them, the electric power consumption of the clock system is particularly large as compared to other systems. It is therefore effective for saving electric power consumption to decrease the electric power consumption in the clock system.
The clock gating technique has been well known as an effective technique for reducing the electric power The of a clock system. In accordance with this prior art technique, data transfer between registers is performed, only when it is necessary, by halting and resuming clock supply by means of a gated clock supplying circuit.
FIG. 3 is a circuit diagram showing a clock supplying circuit for the clock supplying a gated clock signal in accordance with the prior art technique. Enable buffer cells 72 are inserted between a root driver cell 71 and the register (flip-flop) 73 in order to form a tree structure. The respective enable buffer cells 72 are controlled by enable signals E1 to E3. Meanwhile, in this case, there is a branch through which the registers 73 are connected directly to the root driver cell 71.
In accordance with this gated clock circuit technique, the clock supplying circuit is implemented with the buffer cells 72 each of which outputs the logic product or sum of the clock signal CLK and the control signal E1, E2 or E3 called an enable signal are used. In the case as illustrated in FIG. 3, each enable buffer cell 72 outputs the logic product.
Accordingly, for example, only when the enable signals E1 is logic one, xe2x80x9c1xe2x80x9d, the clock signal from the root driver cell 71 is passed to the register 73 at the end of sub-trees through the enable buffer cells 72. In the description, the clock signal as passed through the enable buffer cell is simply called as xe2x80x9cthe clock signalxe2x80x9d while the clock signal as originally input to the root driver cell 71 is called as xe2x80x9cthe clock signal CLKxe2x80x9d.
FIG. 4 is a circuit diagram showing the operation of the enable buffer cell 72 for outputting the logic product of two input signals as described above. Each enable buffer cell 72 receives the enable signals EN through one input terminal thereof and the clock signal through the other input terminal and supplies its output signal to the registers 73. The clock signal is transferred through the buffer cells 72 only when the enable signals E1 is logic one xe2x80x9c1xe2x80x9d, but not transferred through the buffer cells 72 when the enable signals E1 is logic zero xe2x80x9c0xe2x80x9d. In the case that the enable buffer cell is designed for outputting the logic sum of two input signals, the clock signal is transferred through the buffer cell only when the enable signals E1 is logic zero xe2x80x9c0xe2x80x9d, but not transferred through the buffer cell when the enable signals E1 is logic one xe2x80x9c1xe2x80x9d.
As explained in the above, it is possible to dispense with unnecessary transmission of the clock signal by inserting the buffer cells of logic AND or OR receiving the enable signals and the clock signal together with a combinational circuit for generating the enable signals EN, and therefore to reduce the electric power consumption.
On the other hand, after generating appropriate enable signals, there might be further problems as follows. Namely, it is not yet confirmed whether or not the clock skew can be minimized in order to guarantee normal operation at a predetermined operating frequency while a number of different enable signals are used in the same clock system.
Conventionally, a sub-tree is formed with the buffer cells under control of the same enable signal in order to minimize the clock skew. In this case, however, a problem remains about how to minimize the differential delay time among the respective sub-trees. One of solutions will be explained with the circuit as illustrated in FIG. 3. Since the driving power of the circuit is not sufficient, buffer cells 74 are inserted in order to form a tree structure as illustrated in FIG. 5. In the case as illustrated in FIG. 5, the sub-tree through the enable buffer cell 72 under control of the enable signals E1 is the sub-tree Tm having the largest the delay time.
After determining the sub-tree Tm having the largest the delay time, the other sub-trees than the sub-tree Tm are provided with auxiliary buffer cells in order that the delay times thereof agree with that of the sub-tree Tm. For example, a number of transfer buffer cells are inserted after the buffer cells 74 under control of the enable signals E2 and E3 in a multi-stage fashion, or high power buffer cells 74a are inserted as in the lowest path in the illustration of FIG. 6. The insertion is made for the purpose of modifying the tree structure in order to minimize the clock skew by increasing the delay times In this case, the delay time may be increased also by decreasing the driving power of the buffer cells. In the case of the lowest path in the illustration, if three identical buffer cells are inserted, the delay time is too long. Two of the buffer cells 4a are therefore designed with higher driving power in order to decrease the delay time.
However, the driving power of a buffer cell can be adjusted only in steps, while the incremental number of stages as increased by insertion is also stepwise of course, so that it is difficult to finely adjust the delay time for the respective sub-tree. Accordingly, as the number of sub-trees of the respective enable signals increases as illustrated in FIG. 6, it is furthermore difficult to minimize the differential delay time among the respective sub-trees. The clock gating circuit designing technique implies complexity and prolonged development times as required.
The present invention has been made in order to solve the shortcomings as described above. It is an object of the present invention to provide a computer aided design system and a method for clock gated logic circuits effective to reduce the electric power consumption.
It is another object of the present invention to provide a clock supplying circuit and method for designing the same for clock gated logic circuits effective to minimize the clock skew.
It is a further object of the present invention to provide an enable buffer cell for outputting logic sum and an enable buffer cell for outputting logic product which have substantially same characteristics in terms of the signal delay.
In brief, the above and other objects and advantages of the present invention are provided by a new and improved computer aided design system for clock gated logic circuits comprising:
a circuit information storing section for storing information about a clock gated logic circuit under the design;
a halt condition extraction section for extracting, by the use of said information about the clock gated logic circuit, a halt condition under which a clocked circuit driven by a clock signal can halt with no clock signal supplied;
an enable signal candidate generation section for generating enable signal candidates, from said halt condition, which can be used as enable signals in the clock gated logic circuit;
an analysis section provided to analyze the clock gated logic circuit in order to obtain information about a delay time of signal transmission and electric power consumption reduction if respective one of enable signal candidates is used as an enable signal of a clock gating circuit inserted in the clock gated logic circuit under the design;
an enable signal candidate information storing section provided to store enable signal candidate information including the result of the analysis conducted by said analysis section;
a design restriction input section provided to input restrictions upon a delay time of signal transmission of the clock gated logic circuit under the design;
an enable signal selection section provided to select an appropriate one of the enable signal candidates which satisfy the restriction, by the use of said enable signal candidate information and said restriction information.
a clock gating circuit addition section provided to add a clock gating circuit activated with the enable signal as selected by said enable signal selection section to the clock gated logic circuit under the design.
Also, in accordance with a preferred embodiment of the present invention, said clocked circuit is a storage element to which data is loaded in synchronism with the clock signal while said halt condition extraction section is a non-load condition extraction section provided to extract the non-load condition under which it is not required to load data to said storage element.
Also, in accordance with a preferred embodiment of the present invention, said analysis section provided to analyze the clock gated logic circuit in order to obtain information also about an incremental area if respective one of enable signal candidates is used as an enable signal of the clock gating circuit in the clock gated logic circuit under the design.
Also, a preferred embodiment of the present invention is provided with a non-load condition input section provided to manually input non-load conditions under which it is not required to load data to said storage element.
Also, in accordance with a preferred embodiment of the present invention, the enable signal candidate information stored in said enable signal candidate information storing section is given in the form of a graph or a table on a CRT in order to make it possible to manually select an appropriate enable signal.
In accordance with a further aspect of the present invention, a computer aided design method for designing clock gated logic circuits comprising the steps of:
extracting, by the use of information about a clock gated logic circuit under the design, a halt condition under which a clocked circuit driven by a clock signal can halt with no clock signal supplied;
generating enable signal candidates, from said halt condition, which can be used as enable signals in the clock gated logic circuit;
analyzing the clock gated logic circuit in order to obtain information about a delay time of signal transmission and electric power consumption reduction if respective one of enable signal candidates is used as an enable signal of a clock gating circuit inserted in the clock gated logic circuit under the design;
storing enable signal candidate information including the result of the analysis conducted by said analysis step in a information store means;
selecting an appropriate one of the enable signal candidates which satisfy given restrictions regarding a delay time of signal transmission in the clock gated logic circuit under the design, by the use of said enable signal candidate information;
adding the clock gating circuit activated with the enable signal as selected by said enable signal selection step to the clock gated logic circuit under the design.
Also, in accordance with a preferred embodiment of the present invention, the clocked circuit is a storage element to which data is input in synchronism with the clock signal and said halt condition is a non-load condition.
Also, a preferred embodiment of the present invention is provided with a step of manually inputting a non-load condition under which it is not required to load data to said storage element.
Also, in accordance with a preferred embodiment of the present invention, the enable signal candidate information stored in said enable signal candidate information storing step is given in the form of a graph or a table on a CRT in order to make it possible to manually select an appropriate enable signal.
In accordance with a further aspect of the present invention, a computer program embodied on a computer-readable medium for designing clock gated logic circuits, said program comprising:
means for extracting, by the use of information about a clock gated logic circuit under the design, a halt condition under which a clocked circuit driven by a clock signal can halt with no clock signal supplied;
means for generating enable signal candidates, from said halt condition, which can be used as enable signals in the clock gated logic circuit;
means for analyzing the clock gated logic circuit in order to obtain information about a delay time of signal transmission and electric power consumption reduction if respective one of enable signal candidates is used as an enable signal of a clock gating circuit inserted in the clock gated logic circuit under the design;
means for storing enable signal candidate information including the result of the analysis conducted by said analysis step in a information store means;
means for selecting an appropriate one of the enable signal candidates which satisfy given restrictions regarding a delay time of signal transmission in the clock gated logic circuit under the design, by the use of said enable signal candidate information;
means for adding the clock gating circuit activated with the enable signal as selected by said enable signal selection step to the clock gated logic circuit under the design.
In accordance with a further aspect of the present invention, a clock supplying circuit comprising:
a root driver cell for receiving a clock signal; and
a plurality of enable buffer cells each of which is provided with a first input terminal for receiving the clock signal, a second input terminal for receiving an enable signal, an output terminal for outputting the clock signal only when the enable signal as received by the second input terminal is active, said plurality of enable buffer cells being connected with each other in the form of a multi-stage buffering tree structure originating from said root driver cell;
a plurality of clocked circuits for receiving the clock signal from said root driver cell through said enable buffer cells;
wherein said enable buffer cells include a first enable buffer cell receiving a variable signal as the enable signal and a second enable buffer cell receiving a fixed signal as the enable signal which is constantly active.
Also, in accordance with a preferred embodiment of the present invention, the number of said enable buffer cells through which said clock signal is transferred from said the root driver cell to each of said clocked circuits is equal to the number of said enable buffer cells to another of said clocked circuits.
Also, in accordance with a preferred embodiment of the present invention, all of said the enable buffer cells have been designed in a substantially same configuration.
Also, in accordance with a preferred embodiment of the present invention, a fixed signal is given, as the enable signal, to those of said enable buffer cells that are located in the downstream side of one of said enable buffer cells to which the enable signal has been already given.
Also, in accordance with a preferred embodiment of the present invention, said root driver cell is directly connected to said one of said enable buffer cells to which the enable signal is given without any intervening one of said enable buffer cells.
Also, in accordance with a preferred embodiment of the present invention, said root driver cell is connected to said one of said enable buffer cells to which the enable signal is given only through one or more buffer of said second enable buffer cells.
Also, in accordance with a preferred embodiment of the present invention, there are at least one enable buffer cell driven by a first variable enable signal and at least one enable buffer cell driven by a second enable signal which is different from the first variable enable signal.
Also, in accordance with a preferred embodiment of the present invention, all of said the clocked circuits are provided with preceding enable buffer cells, said preceding enable buffer cells including at least one of said first enable buffer cells and at least one of said second enable buffer cells.
In accordance with a further aspect of the present invention, a method of designing a clock supplying circuit by the use of enable signals comprising the steps of:
locating enable buffer cells controlled by enable signals in order to form a multi-stage buffering tree structure and roughly determine clock signal paths.
checking whether or not the load capacitance of each of the respective enable signals is within the driving capability of a driver cell outputting said each of the respective enable signals and whether or not there is an unsatisfied timing constraint upon the enable signals;
resolving each unsatisfied timing constraint by inserting at least one buffer for reinforcing the enable signal or replacing the circuit design of said driver cell by a more powerful circuit design.
adjusting wirings of the clock signal paths in order to eliminate imbalance among delay times for respective clock signal paths in the multi-stage buffering tree structure; and
determining the other signal paths including the enable signals.
Also, a preferred embodiment of the present invention is provided with the step of separating overlaid cells.
In accordance with a further aspect of the present invention, an enable buffer cell comprising:
a first inverter provided with an input terminal for receiving an input signal and an output terminal outputting an inverted signal of said input signal;
a transmission gate provided with an input terminal for receiving the inverted signal output from said first inverter, a pair of control terminals for receiving a control signal and an inverted signal of said control signal and an output terminal for outputting the output signal of said first inverter;
a second inverter provided with an input terminal for receiving the output signal of said transmission gate and an output terminal outputting an inverted signal of said output signal of said transmission gate; and
a MOS transistor connected between the input terminal of said second inverter and a source of a fixed signal and receiving said enable signal through a gate terminal in order to give said fixed signal to said second inverter when said transmission gate is turned off.
Also, in accordance with a preferred embodiment of the present invention, said MOS transistor is a p-type MOS transistor whose drain terminal is connected to the input terminal of said second inverter, source terminal is connected to a power source, and gate terminal is given said enable signal.
Also, in accordance with a preferred embodiment of the present invention, said MOS transistor is an n-type MOS transistor whose source terminal is connected to the input terminal of said second inverter, drain terminal is connected to ground, and gate terminal is given said enable signal.